The present invention relates in general to CMOS opamp circuits, and in particular, to CMOS opamps with a class A/B output stage capable of driving high capacitive loads.
An example of a prior art CMOS opamp with a class A/B output stage can be found in the Journal of Solid State Circuits, Dec. 1987, page 1087, FIG. 7(a) of the article "A programmable Gain/Loss Circuit," by J. Babanezhad and R . Gregorian. The prior art opamp includes a folded cascode gain stage followed by a class A/B output stage. This opamp was designed for use in a programmable gain/loss circuit where high gain and large bandwidth were required for an opamp driving capacitive loads of relatively modest size.
While this prior art opamp performs well for the particular application, it suffers from several disadvantages. First, in many applications, opamps are required to drive very large capacitive loads where the load capacitor provides the dominant pole. Often, under such circumstances, the Miller capacitance and the zero-nulling resistor are removed to allow the load capacitance to provide the necessary frequency compensation. However, the pole created by the combination of the high impedance node at the output of the folded cascode input stage and the large gate capacitances (of output transistors) connected to that node, makes it very difficult to stabilized this opamp with a load capacitor.
Second, in applications requiring very large output devices this opamp would experience slew rate limiting. This is due to the output of the folded cascode stage directly connecting to the gate of a PMOS pull-up transistor that drives the output node. For a larger output transistor (i.e. higher gate capacitance), therefore, the folded cascode must provide larger amounts of current. However, increased currents reduce the impedance at the output of the folded cascode, which results in loss of overall gain.
Another disadvantage of this prior art opamp is its limited current sinking capability. The biasing of the output stage allows the gate of the common-source PMOS transistor driving the output node to have a large voltage swing, while the common-source NMOS transistor driving the output experiences a very limited voltage swing at its gate. As a result, the output stage can source much more current than it can sink.